Rex N. Fisher                             Computer Science and Engineering Department, BYU-Idaho

ECE 340 Digital Systems Design

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[ECE 340 Assignments]     [ECE 340 Course Outline] 

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IMPORTANT: More details regarding schedules, assignments, and policies are available to registered students on I-Learn.  These items are subject to change, but students will be given advance notification of any changes.

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Course Description:

 

Hierarchical design of digital systems.  Synchronous state machine design, including the use of ROMs, one-hot count sequences, and other variations.  Asynchronous state machine design.  Circuit synthesis and simulation using the Verilog hardware description language.  Circuit implementation field programmable gate arrays (FPGAs).  A technical report and presentation is required.  Laboratory exercises are included.

 

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Course Objectives:

 

At the conclusion of this course students will be able to:

1. Design synchronous and asynchronous sequential circuits.
2. Design and simulate digital systems, including the creation of custom hierarchical blocks, with the Verilog hardware description language.
3. Use FPGAs to implement digital systems.
4. Work on a team to solve an engineering problem.
5. Make technical presentations.
6. Write technical reports.

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Course Prerequisite:

 

ECE/CompE 224 Fundamentals of Digital Systems

 

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Required Texts:

 

Verilog-A Language Reference Manual  This is a Verilog Hardware Description Language (HDL) language reference manual.

 

IEEE Editorial Style Manual  This style manual provides editorial guidelines for IEEE Transactions, Journals, and Letters. The technical report that accompanies your presentation must be written ini the format of an IEEE journal article.  See an example of an IEEE paper.

  

Recommended Texts:

 

Verilog Quick Refernce Guide

 

Designing Digital Systems by Nelson (Published by BYU Academic Publishing and available in the BYU and BYU-Idaho bookstores.)  -OR-  any other textbook on digital logic design.

 

The Chicago Manual of Style  For guidance on grammar and usage not included in the IEEE Editorial Style Manual.

 

Xilinx ISE 6.202i Tutorial by Michael Ciletti.  This is for an older version of ISE than the one currently in use, but most of it is still useful.

 

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Required/Recommended Software: 

 

FREE Xilinx ISE WebPACK: Software to implement Verilog (or VHDL) designs on Xilinx FPGAs.  Read the Xilinx ISE 8.2i Quick Start Tutorial by Xilinx.

 

PSpice Student Version: This is the student version of the Cadence circuit simulation software available in our labs.  This program makes it easy to include schematic diagrams in your lab reports.  Be sure to also download the documentation from this web site.

 

CircuitMaker: This is similar to PSpice (above).  While it is a little less powerful, it is easier to use.  This program also makes it easy to include schematic diagrams in your lab reports.  Use this Screen Capture Software  to copy them from CircuitMaker to your document.

 

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Class Score Calculation:

 

Exams & Quizzes:      30%
Homework:                  10%
Lab Experiments:       20%
Project:                         10%
Presentation/Report:  20%
Teaching/Learning:    10%

Total:                           100%

 

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Grading Scale:

 

93% - 100%  A
90% - 92%    A-
87% - 89%    B
83% - 86%    B
80% - 82%    B-
77% - 79%    C
73% - 76%    C
70% - 72%    C-
67%- 69%     D
63% - 66%    D
60% - 62%    D-