P8 CPU Documentation -- Appendix 7.1

Design and Implementation of a Simple 8-Bit CPU

7.1 Appendix: Comprehensive Description of P8 CPU Instruction Set

Each instruction has an 8-bit opcode. The eight bits are divided into two fields: 1) the operation; and 2) the addressing mode.

All instructions that use register addressing or indirect addressing require only one byte. A second byte is required for the other two addressing modes. The second byte of a direct instruction contains the 8-bit address, and the second byte of an immediate instruction specifies the immediate data. See Figure 7.2.1.

-----------------
|X|X|X|X|X|Y|Y|Y| 8-Bit Opcode
-----------------
-----------------
|Z|Z|Z|Z|Z|Z|Z|Z| 8-Bit Address or Immediate Data
-----------------

Figure 7.1.1: Instruction Format

The operation is encoded in the 5-bit field labeled XXXXX:

5-Bit Operation Code Instruction Type Instruction Category

00001 IN Input/Output
00010 OUT Input/Output

00100                      JMP                  Program Control
00101                      JNZ                  Program Control
00110                      JZ                   Program Control
00111                      CMP                  Program Control

01000                      LDA                  Data Transfer
01001                      LDR                  Data Transfer
01010                      STA                  Data Transfer
01011                      STR                  Data Transfer

01100                      ADD                  Arithmetic
01101                      SUB                  Arithmetic
01110                      DEC                  Arithmetic

10000                      OR                   Logical
10001                      INV                  Logical
10010                      SHL                  Logical

The addressing mode is encoded in the 3-bit field labeled YYY:

3-Bit Code Addressing Mode Data Location000 Direct Memory or Port Address in Byte 2

001 Not Used ---

010 Register A Register

011 Register R Register

100 Indirect Memory or Port Address in R Register

101 Not Used ---

110 Immediate Byte 2 of Instruction

111 Not Used ---

Complete P8 instruction set:

Hexadecimal P8 Assembly Hexadecimal P8 Assembly
Object Code Source Code Object Code Source Code

    08, address    IN address          60, address    ADD address
    0C             IN P                62             ADD A
                                       63             ADD R
    10, address    OUT address         64             ADD M
    14             OUT P               66, data       ADD I data

    20, address    JMP address         68, address    SUB address
    23             JMP R               6A             SUB A
                                       6B             SUB R
    28, address    JNZ address         6C             SUB M
    2B             JNZ R               6E, data       SUB I data

    30, address    JZ address          70, address    DEC address
    33             JZ R                72             DEC A
                                       73             DEC R
    38, address    CMP address         74             DEC M
    3A             CMP A               76, data       DEC I data
    3B             CMP R
    3C             CMP M               80, address    OR address
    3E, data       CMP I data          82             OR A
                                       83             OR R
    40, address    LDA address         84             OR M
    42             LDA A               86, data       OR I data
    43             LDA R
    44             LDA M               88, address    INV address
    46, data       LDA I data          8A             INV A
                                       8B             INV R
    48, address    LDR address         8C             INV M
    4A             LDR A               8E, data       INV I, data
    4B             LDR R
    4C             LDR M               90, address    SHL address
    4E, data       LDR I data          92             SHL A
                                       93             SHL R
    50, address    STA address         94             SHL M
    54             STA M               96, data       SHL, data

    58, address    STR address         00             FETCH
    5C             STR M

FETCH Opcode Fetch

NOTE: FETCH is not generally used explicitly by programmers. Instead, it is automatically invoked by the CPU to read the next instruction that is to be executed.

It is described here because it is part of every P8 CPU instruction. The first three clock cycles of any instruction are used by FETCH.

Operation: IR <-- MEM(IP); IP <-- IP + 1

Encoding: 00000000 (00h)

Clock Cycles: 3

Description: The contents of the memory address pointed to by the Instruction Pointer (IP) are transferred to the Instruction Register (IR). IP increments.

Example:

    Preconditions: Address 06h = 54h
                   IR = 70h
                   IP = 06h

Instruction: FETCH

Postconditions: IR = 54h
IP = 07h

Micro-Instructions:

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

IR <-- DR

ADD address Add Direct To A Register

Addressing Mode: Direct

Operation: A <-- A + MEM(address); IP <-- IP + 2

Encoding:

Byte 1: 01100 000 (60h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are added to the contents of the A Register. The result is stored in the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: ADD 10h

Postconditions: A Register = 0Ah
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

    DR <-- Memory Data; IP <-- IP + 1;
    Memory Address <-- AR; Assert MEMR

    OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR; Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) + ALU(B);
    A <-- ALU(F)

ADD A Add A Register To A Register

Addressing Mode: Register

Operation: A <-- A + A; IP <-- IP + 1

Encoding: 01100 010 (62h)

Clock Cycles: 4

Description: The contents of the A Register are added to the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: ADD A

Postconditions: A Register = 0Ch
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- A;
    ALU(F) <-- ALU(A) + ALU(B);
    A <-- ALU(F)

ADD R Add R Register To A Register

Addressing Mode: Register

Operation: A <-- A + R; IP <-- IP + 1

Encoding: 01100 011 (63h)

Clock Cycles: 4

Description: The contents of the R Register are added to the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: ADD R

Postconditions: A Register = 0Ah
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- R;
    ALU(F) <-- ALU(A) + ALU(B);
    A <-- ALU(F)

ADD M Add Indirect To A Register

Addressing Mode: Indirect

Operation: A <-- A + MEM(R); IP <-- IP + 1

Encoding: 01100 100 (64h)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are added to the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: ADD M

Postconditions: A Register = 0Ah
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) + ALU(B);
    A <-- ALU(F)

ADD I data Add Immediate To A Register

Addressing Mode: Immediate

Operation: A <-- A + data; IP <-- IP + 2

Encoding:

Byte 1: 01100 110 (66h)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are added to the contents of the A Register. The result is stored in the A Register. IP increments 2 times.

Example:

    Preconditions: A Register = 06h
                   IP = 00h

    Instruction: ADD 10h

Postconditions: A Register = 16h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) + ALU(B);
    A <-- ALU(F)

CMP address Compare Direct With A Register

Addressing Mode: Direct

Operation: if A - MEM(address) = 0: Z <-- 1; IP <-- IP + 2

Encoding:

Byte 1: 00111 000 (38h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are compared (by subtraction) to the A Register. If they are equal, the Zero Flag is set, otherwise it is reset. IP increments 2 times.

Example:

    Preconditions: Address 10h = 06h
                   A Register = 06h
                   IP = 00h
                   Z = don=t care

Insruction: CMP 10h

    Postconditions: A Register = 06h
                    IP = 02h
                    Z = 1h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

ALU(A) <-- A; ALU(B) <-- DR;
ALU(F) <-- ALU(A) - ALU(B); Z <-- Zero Condition Bit

CMP A Compare A Register With A Register

Addressing Mode: Register

Operation: Z <-- 1; IP <-- IP + 1

Encoding: 00111 010 (3Ah)

Clock Cycles: 4

Description: The contents of the A Register are subtracted from the contents of the A Register. The result is always zero, which sets the Zero Flag. The result is discarded. IP increments.

Example:

    Preconditions: A Register = 06h
                   IP = 00h
                   Z = don=t care

Instruction: CMP A

    Postconditions: A Register = 06h
                    IP = 01h
                    Z = 1h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- A;
    ALU(F) <-- ALU(A) - ALU(B);
    Z <-- 1

CMP R Compare R Register With A Register

Addressing Mode: Register

Operation: if A - R = 0: Z <-- 1; IP <-- IP + 1

Encoding: 00111 011 (3Bh)

Clock Cycles: 4

Description: The contents of the R Register are subtracted from the contents of the A Register. If the result is zero, the Zero Flag is set, otherwise it is reset. The result is discarded. IP increments.

Example:

    Preconditions: R Register = 06h
                   A Register = 06h
                   IP = 00h
                   Z = don=t care

Instruction: CMP R

    Postconditions: R Register = 06h
                    A Register = 06h
                    IP = 01h
                    Z = 1h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- R;
    ALU(F) <-- ALU(A) - ALU(B);
    Z <-- Zero Condition Bit

CMP M Compare Indirect With A Register

Addressing Mode: Indirect

Operation: if A - MEM(R) = 0: Z <-- 1; IP <-- IP + 1

Encoding: 00111 100 (3Ch)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are subtracted from the contents of the A Register. If the result is zero, the Zero Flag is set, otherwise it is reset. The result is discarded. IP increments.

Example:

    Preconditions: Address 10h = 06h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h
                   Z = don=t care

Instruction: CMP M

    Postconditions: A Register = 06h
                    IP = 01h
                    Z = 1h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) - ALU(B);
    Z <-- Zero Condition Bit

CMP I data Compare Immediate With A Register

Addressing Mode: Immediate

Operation: if A - data = 0: Z <-- 1; IP <-- IP + 2

Encoding:

Byte 1: 00111 110 (3Eh)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are subtracted from contents of the A Register. If the result is zero, the Zero Flag is set, otherwise it is reset. The result is discarded. IP increments 2 times.

Example:

    Preconditions: A Register = 06h
                   IP = 00h
                   Z = don=t care

Instruction: CMP 06h

    Postconditions: A Register = 06h
                    IP = 02h
                    Z = 1h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;

Memory Address <-- AR; Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) - ALU(B);
    Z <-- Zero Condition Bit

DEC address Decrement Direct & Move To A Register

Addressing Mode: Direct

Operation: A <-- MEM(address) - 1; IP <-- IP + 2

Encoding:

Byte 1: 01110 000 (70h)

Byte 2: 8-bit address

Clock Cycles: 11

Description: The contents of the memory address in byte 2 are transferred to the A Register and decremented. The result is stored in the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: DEC 10h

Postconditions: A Register = 03h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR; Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- ALU(A) - 1

A <-- ALU(F)

DEC A Decrement A Register

Addressing Mode: Register

Operation: A <-- A - 1; IP <-- IP + 1

Encoding: 01110 010 (72h)

Clock Cycles: 4

Description: The contents of the A Register are decremented. The result is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: DEC A

Postconditions: A Register = 05h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

ALU(A) <-- A; ALU(F) <-- ALU(A) - 1; A <-- ALU(F)

DEC R Decrement R Register

Addressing Mode: Register

Operation: R <-- R - 1; IP <-- IP + 1

Encoding: 01110 011 (73h)

Clock Cycles: 7

Description: The contents of the R Register are transferred to the A Register. The A Register is decremented. The result is moved to the R Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: DEC R

    Postconditions: R Register = 03h
                    A Register = 03h
                    IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

A <-- R

ALU(A) <-- A; ALU(F) <-- ALU(A) - 1

A <-- ALU(F)

R <-- A

DEC M Decrement Indirect & Move To A Register

Addressing Mode: Indirect

Operation: A <-- MEM(R) - 1; IP <-- IP + 1

Encoding: 01110 100 (74h)

Clock Cycles: 9

Description: The contents of the memory address pointed to by the R Register are transferred to the A Register. The A Register is decremented. The result is stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: DEC M

Postconditions: A Register = 03h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- ALU(A) - 1

A <-- ALU(F)

DEC I data Decrement Immediate & Move To A Register

Addressing Mode: Immediate

Operation: A <-- data - 1; IP <-- IP + 2

Encoding:

Byte 1: 01110 110 (76h)

Byte 2: 8-bit data

Clock Cycles: 8

Description: The data in byte 2 are transferred to the A Register. The A Register is decremented. The result is stored in the A Register. IP increments 2 times.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: DEC 10h

Postconditions: A Register = 0Fh
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- ALU(A) - 1

A <-- ALU(F)

IN address Read Port Direct

Addressing Mode: Direct

Operation: A <-- PORT(address); IP <-- IP + 2

Encoding:

Byte 1: 00001 000 (08h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the port address in byte 2 are transferred to the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: IN 10h

Postconditions: A Register = 04h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Port Address <-- AR; Assert IOR

DR <-- Port Data; Port Address <-- AR; Assert IOR

A <-- DR

IN P Read Port Indirect

Addressing Mode: Indirect

Operation: A <-- PORT(R); IP <-- IP + 1

Encoding: 00001 100 (0Ch)

Clock Cycles: 7

Description: The contents of the port address pointed to by the R Register are transferred to the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: IN P

Postconditions: A Register = 04h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Port Address <-- AR; Assert IOR

DR <-- Port Data; Port Address <-- AR; Assert IOR

A <-- DR

INV address Invert Direct & Move To A Register

Addressing Mode: Direct

Operation: A <-- [MEM(address)]=; IP <-- IP + 2

Encoding:

Byte 1: 10001 000 (88h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address are inverted and stored in the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

    Instruction: INV 10h

    Postconditions: A Register = FBh
                    IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

ALU(B) <-- DR; ALU(F) <-- [ALU(B)]';
A <-- ALU(F)

INV A Invert A Register

Addressing Mode: Register

Operation: A <-- [A]=; IP <-- IP + 1

Encoding: 10001 010 (8Ah)

Clock Cycles: 4

Description: The contents of the A Register are inverted. The result is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 04h
IP = 00h

Instruction: INV A

Postconditions: A Register = FBh
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

ALU(B) <-- A; ALU(F) <-- [ALU(B)]';
A <-- ALU(F)

INV R Invert R Register

Addressing Mode: Register

Operation: R <-- [R]=; IP <-- IP + 1

Encoding: 10001 011 (8Bh)

Clock Cycles: 5

Description: The contents of the R Register are inverted and the results are moved to the R Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: INV R

    Postconditions: R Register = FBh
                    A Register = FBh
                    IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

ALU(B) <-- R; ALU(F) <-- [ALU(B)]';
A <-- ALU(F)

R <-- A

INV M Invert Indirect & Move To A Register

Addressing Mode: Indirect

Operation: A <-- [MEM(R)]=; IP <-- IP + 1

Encoding: 10001 100 (8Ch)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are inverted and stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: INV M

Postconditions: A Register = FBh
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

ALU(B) <-- DR; ALU(F) <-- [ALU(B)]';
A <-- ALU(F)

INV I data Invert Immediate & Move To A Register

Addressing Mode: Immediate

Operation: A <-- [data]=; IP <-- IP + 2

Encoding:

Byte 1: 10001 110 (8Eh)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are inverted and stored in the A Register. IP increments 2 times.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: INV 04h

Postconditions: A Register = FBh
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

ALU(B) <-- DR; ALU(F) <-- [ALU(B)]';
A <-- ALU(F)

JMP address Jump Direct

Addressing Mode: Direct

Operation: IP <-- address

Encoding:

Byte 1: 00100 000 (20h)

Byte 2: 8-bit address

Clock Cycles: 6

Description: The address in byte 2 is transferred to the Instruction Pointer.

Example:

Preconditions: Address 10h = 04h
IP = 00h

Instruction: JMP 10h

Postconditions: IP = 04h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

IP <-- DR

JMP R Jump Indirect

Addressing Mode: Register

Operation: IP <-- R

Encoding: 00100 011 (23h)

Clock Cycles: 4

Description: The contents of the R Register are transferred to the Instruction Pointer.

Example:

Preconditions: R Register = 10h
IP = 00h

Instruction: JMP R

Postconditions: IP = 10h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

IP <-- R

JNZ address Jump Direct If Not Zero

Addressing Mode: Direct

Operation: if Z = 0: IP <-- address

Encoding:

Byte 1: 00101 000 (28h)

Byte 2: 8-bit address

Clock Cycles:

6 if Z = 0

4 if Z = 1

Description: If the Zero Flag is 0, the address in byte 2 is transferred to the Instruction Pointer. If the Zero Flag is 1, the IP is simply incremented to the next instruction.

Example:

Preconditions: IP = 00h
Z = 0h

Instruction: JNZ 10h

Postconditions: IP = 10h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

if Z = 0: JMP address

if Z = 1: IP <-- IP + 1

JNZ R Jump If Not Zero

Addressing Mode: Register

Operation: if Z = 0: IP <-- R

Encoding: 00101 011 (2Bh)

Clock Cycles: 4

Description: If the Zero Flag is 0, the contents of the R Register are transferred to the Instruction Pointer. If the Zero Flag is 1, no operation is performed.

Example:

    Preconditions: IP = 00h
                   R = 10h
                   Z = 0h

Instruction: JNZ R

Postconditions: IP = 10h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

if Z = 0: JMP R

if Z = 1: No Operation

JZ address Jump Direct If Zero

Addressing Mode: Direct

Operation: if Z = 1: IP <-- address

Encoding:

Byte 1: 00110 000 (30h)

Byte 2: 8-bit address

Clock Cycles:

6 if Z = 1

4 if Z = 0

Description: If the Zero Flag is 1, the address in byte 2 is transferred to the Instruction Pointer. If the Zero Flag is 0, the IP is simply incremented to the next instuction.

Example:

Preconditions: IP = 00h
Z = 1h

Instruction: JZ 10h

Postconditions: IP = 10h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

if Z = 1: JMP address

if Z = 0: IP <-- IP + 1

JZ R Jump If Zero

Addressing Mode: Register

Operation: if Z = 1: IP <-- R

Encoding: 00110 011 (33h)

Clock Cycles: 4

Description: If the Zero Flag is 1, the contents of the R Register are transferred to the Instruction Pointer. If the Zero Flag is 0, no operation is performed.

Example:

    Preconditions: IP = 00h
                   R = 10h
                   Z = 1h

Instruction: JZ R

Postconditions: IP = 10h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

if Z = 1: JMP R

if Z = 0: No Operation

LDA address Load A Register Direct

Addressing Mode: Direct

Operation: A <-- MEM(address); IP <-- IP + 2

Encoding:

Byte 1: 01000 000 (40h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are transferred to the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: LDA 10h

Postconditions: A Register = 04h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

A <-- DR

LDA A Load A Register With A Register

Addressing Mode: Register

Operation: A <-- A; IP <-- IP + 1

Encoding: 01000 010 (42h)

Clock Cycles: 4

Description: The contents of the A Register are left in the A Register. This instruction does not change the state of the CPU, except to increment the IP.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: LDA A

Postconditions: A Register = 06h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

No Operation

LDA R Load A Register With R Register

Addressing Mode: Register

Operation: A <-- R; IP <-- IP + 1

Encoding: 01000 011 (43h)

Clock Cycles: 4

Description: The contents of the R Register are transferred to the A Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: LDA R

Postconditions: A Register = 04h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

A <-- R

LDA M Load A Register Indirect

Addressing Mode: Indirect

Operation: A <-- MEM(R); IP <-- IP + 1

Encoding: 01000 100 (44h)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are transferred to the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: LDA M

Postconditions: A Register = 04h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

A <-- DR

LDA I data Load A Register Immediate

Addressing Mode: Immediate

Operation: A <-- data; IP <-- IP + 2

Encoding:

Byte 1: 01000 110 (46h)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are transferred to the A Register. IP increments 2 times.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: LDA 10h

Postconditions: A Register = 10h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

A <-- DR

LDR address Load R Register Direct

Addressing Mode: Direct

Operation: R <-- MEM(address); IP <-- IP + 2

Encoding:

Byte 1: 01001 000 (48h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are transferred to the R Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 06h
                   IP = 00h

Instruction: LDR 10h

Postconditions: R Register = 04h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

R <-- DR

LDR A Load R Register With A Register

Addressing Mode: Register

Operation: R <-- A; IP <-- IP + 1

Encoding: 01001 010 (4Ah)

Clock Cycles: 4

Description: The contents of the A Register are transferred to the R Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

    Instruction: LDR A

Postconditions: A Register = 04h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

R <-- A

LDR R Load R Register With R Register

Addressing Mode: Register

Operation: R <-- R; IP <-- IP + 1

Encoding: 01001 011 (4Bh)

Clock Cycles: 4

Description: The contents of the R Register are left in the R Register. This instruction does not change the state of the CPU, except to increment the IP.

Example:

Preconditions: R Register = 06h
IP = 00h

Instruction: LDR R

Postconditions: R Register = 06h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

No Operation

LDR M Load R Register Indirect

Addressing Mode: Indirect

Operation: R <-- MEM(R); IP <-- IP + 1

Encoding: 01001 100 (4Ch)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are transferred to the R Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   IP = 00h

Instruction: LDR M

Postconditions: R Register = 04h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

R <-- DR

LDR I data Load R Register Immediate

Addressing Mode: Immediate

Operation: R <-- data; IP <-- IP + 2

Encoding:

Byte 1: 01001 110 (4Eh)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are transferred to the R Register. IP increments 2 times.

Example:

Preconditions: R Register = 06h
IP = 00h

Instruction: LDR 10h

Postconditions: R Register = 10h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

R <-- DR

OR address OR Direct With A Register

Addressing Mode: Direct

Operation: A <-- A OR MEM(address); IP <-- IP + 2

Encoding:

Byte 1: 10000 000 (80h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are ORed with the contents of the A Register. The result is stored in the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 40h
                   A Register = 06h
                   IP = 00h

Instruction: OR 10h

Postconditions: A Register = 46h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) OR ALU(B);
    A <-- ALU(F)

OR A OR A Register With A Register

Addressing Mode: Register

Operation: A <-- A OR A; IP <-- IP + 1

Encoding: 10000 010 (82h)

Clock Cycles: 4

Description: The contents of the A Register are ORed with the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: OR A

Postconditions: A Register = 06h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- A;
    ALU(F) <-- ALU(A) OR ALU(B);
    A <-- ALU(F)

OR R OR R Register With A Register

Addressing Mode: Register

Operation: A <-- A OR R; IP <-- IP + 1

Encoding: 10000 011 (83h)

Clock Cycles: 4

Description: The contents of the R Register are ORed with the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: R Register = 40h
                   A Register = 06h
                   IP = 00h

Instruction: OR R

Postconditions: A Register = 46h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- R;
    ALU(F) <-- ALU(A) OR ALU(B);
    A <-- ALU(F)

OR M OR Indirect With A Register

Addressing Mode: Indirect

Operation: A <-- A OR MEM(R); IP <-- IP + 1

Encoding: 10000 100 (84h)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are ORed with the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 40h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: OR M

Postconditions: A Register = 46h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) OR ALU(B);
    A <-- ALU(F)

OR I data OR Immediate With A Register

Addressing Mode: Immediate

Operation: A <-- A OR data; IP <-- IP + 2

Encoding:

Byte 1: 10000 110 (86h)

Byte 2: 8-bit data

Clock Cycles: 6

Description: The data in byte 2 are ORed with the contents of the A Register. The result is stored in the A Register. IP increments 2 times.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: OR 10h

Postconditions: A Register = 16h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) OR ALU(B);
    A <-- ALU(F)

OUT address Write Port Direct

Addressing Mode: Direct

Operation: PORT(address) <-- A; IP <-- IP + 2

Encoding:

Byte 1: 00010 000 (10h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the A Register are transferred to the Port address in byte 2. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: OUT 10h

Postconditions: Address 10h = 06h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Port Address <-- AR; DR <-- A;
Port Data <-- DR

Port Address <-- AR; Port <-- DR; Assert IOW

Port Address <-- AR; Port Data <-- DR

OUT P Write Port Indirect

Addressing Mode: Indirect

Operation: PORT(R) <-- A; IP <-- IP + 1

Encoding: 00010 100 (14h)

Clock Cycles: 7

Description: The contents of the A Register are transferred to the port address pointed to by the R Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: OUT P

Postconditions: Address 10h = 06h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Port Address <-- AR; DR <-- A;
Port Data <-- DR

Port Address <-- AR; Port Data <-- DR; Assert IOW

Port Address <-- AR; Port Data <-- DR

SHL address Shift Left Direct & Move To A Register

Addressing Mode: Direct

Operation: A <-- [MEM(address)]_6..0 ## 0; IP <-- IP + 2

Encoding:

Byte 1: 10010 000 (90h)

Byte 2: 8-bit address

Clock Cycles: 11

Description: The contents of the memory address are transferred to the A Register and shifted 1 bit left. Zero is shifted into the LSB. The result is stored in the A Register. IP increments twice.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: SHL 10h

Postconditions: A Register = 08h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR; Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- [ALU(A)]_6..0 ## 0

A <-- ALU(F)

SHL A Shift Left A Register

Addressing Mode: Register

Operation: A <-- [A]_6..0 ## 0; IP <-- IP + 1

Encoding: 10010 010 (92h)

Clock Cycles: 4

Description: The contents of the A Register are shifted 1 bit to the left. A zero is shifted into the LSB. The result is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 04h
IP = 00h

Instruction: SHL A

Postconditions: A Register = 08h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

ALU(A) <-- A; ALU(F) <-- [ALU(A)]_6..0 ## 0;
A <-- ALU(F)

SHL R Shift Left R Register

Addressing Mode: Register

Operation: R <-- [R]_6..0 ## 0; IP <-- IP + 1

Encoding: 10010 011 (93h)

Clock Cycles: 7

Description: The contents of the R Register transferred to the A Register and shifted 1 bit to the left. A zero is shifted into the LSB. The result is moved to the R Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: SHL R

    Postconditions: R Register = 08h
                    A Register = 08h
                    IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

A <-- R

ALU(A) <-- R; ALU(F) <-- [ALU(A)]_6..0 ## 0

A <-- ALU(F)

R <-- A

SHL M Shift Left Indirect & Move To A Register

Addressing Mode: Indirect

Operation: A <-- [MEM(R)]_6..0 ## 0; IP <-- IP + 1

Encoding: 10010 100 (94h)

Clock Cycles: 9

Description: The contents of the memory address pointed to by the R Register are transferred into the A Register and shifted 1 bit to the left. A zero is shifted into the LSB. The result is stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: SHL M

Postconditions: A Register = 08h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- [ALU(A)]_6..0 ## 0

A <-- ALU(F)

SHL I data Shift Left Immediate & Move To A Register

Addressing Mode: Immediate

Operation: A <-- [data]_6..0 ## 0; IP <-- IP + 2

Encoding:

Byte 1: 10010 110 (96h)

Byte 2: 8-bit data

Clock Cycles: 8

Description: The data in byte 2 are transferred to the A Register and shifted 1 bit to the left. A zero is shifted into the LSB. The result is stored in the A Register. IP increments 2 times.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: SHL 04h

Postconditions: A Register = 08h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

A <-- DR

ALU(A) <-- A; ALU(F) <-- [ALU(A)]_6..0 ## 0

A <-- ALU(F)

STA address Store A Register Direct

Addressing Mode: Direct

Operation: MEM(address) <-- A; IP <-- IP + 2

Encoding:

Byte 1: 01010 000 (50h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the A Register are transferred to the Memory address in byte 2. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: STA 10h

Postconditions: Address 10h = 06h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR;
DR <-- A; Memory Data <-- DR

Memory Address <-- AR; Memory Data <-- DR;
Assert MEMW

Memory Address <-- AR; Memory Data <-- DR

STA M Store A Register Indirect

Addressing Mode: Indirect

Operation: MEM(R) <-- A; IP <-- IP + 1

Encoding: 01010 100 (54h)

Clock Cycles: 7

Description: The contents of the A Register are transferred to the Memory address pointed to by the R Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: STA M

Postconditions: Address 10h = 06h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR;
DR <-- A; Memory Data <-- DR

Memory Address <-- AR; Memory Data <-- DR;
Assert MEMW

Memory Address <-- AR; Memory Data <-- DR

STR address Store R Register Direct

Addressing Mode: Direct

Operation: MEM(address) <-- R; IP <-- IP + 2

Encoding:

Byte 1: 01011 000 (58h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the R Register are transferred to the Memory address in byte 2. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 06h
                   IP = 00h

Instruction: STR 10h

Postconditions: Address 10h = 06h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR;
DR <-- R; Memory Data <-- DR

Memory Address <-- AR; Memory Data <-- DR;
Assert MEMW

Memory Address <-- AR; Memory Data <-- DR

STR M Store R Register Indirect

Addressing Mode: Indirect

Operation: MEM(R) <-- R; IP <-- IP + 1

Encoding: 01011 100 (5Ch)

Clock Cycles: 7

Description: The contents of the R Register are transferred to the Memory address pointed to by the R Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: STR M

Postconditions: Address 10h = 10h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR;
DR <-- R; Memory Data <-- DR

Memory Address <-- AR; Memory Data <-- DR;
Assert MEMW

Memory Address <-- AR; Memory Data <-- DR

SUB address Subtract Direct From A Register

Addressing Mode: Direct

Operation: A <-- A - MEM(address); IP <-- IP + 2

Encoding:

Byte 1: 01101 000 (68h)

Byte 2: 8-bit address

Clock Cycles: 9

Description: The contents of the memory address in byte 2 are subtracted from the contents of the A Register. The result is stored in the A Register. IP increments 2 times.

Example:

    Preconditions: Address 10h = 04h
                   A Register = 06h
                   IP = 00h

Instruction: SUB 10h

Postconditions: A Register = 02h
IP = 02h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

AR <-- IP; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; IP <-- IP + 1;
Memory Address <-- AR; Assert MEMR

OR <-- DR

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) - ALU(B);
    A <-- ALU(F)

SUB A Subtract A Register From A Register

Addressing Mode: Register

Operation: A <-- A - A; IP <-- IP + 1

Encoding: 01101 010 (6Ah)

Clock Cycles: 4

Description: The contents of the A Register are subtracted from the contents of the A Register. The result (always zero) is stored in the A Register. IP increments.

Example:

Preconditions: A Register = 06h
IP = 00h

Instruction: SUB A

Postconditions: A Register = 00h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- A;
    ALU(F) <-- ALU(A) - ALU(B);
    A <-- ALU(F)

SUB R Subtract R Register From A Register

Addressing Mode: Register

Operation: A <-- A - R; IP <-- IP + 1

Encoding: 01101 011 (6Bh)

Clock Cycles: 4

Description: The contents of the R Register are subtracted from the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: R Register = 04h
                   A Register = 06h
                   IP = 00h

Instruction: SUB R

Postconditions: A Register = 02h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

    ALU(A) <-- A; ALU(B) <-- R;
    ALU(F) <-- ALU(A) - ALU(B);
    A <-- ALU(F)

SUB M Subtract Indirect From A Register

Addressing Mode: Indirect

Operation: A <-- A - MEM(R); IP <-- IP + 1

Encoding: 01101 100 (6Ch)

Clock Cycles: 7

Description: The contents of the memory address pointed to by the R Register are subtracted from the contents of the A Register. The result is stored in the A Register. IP increments.

Example:

    Preconditions: Address 10h = 04h
                   R Register = 10h
                   A Register = 06h
                   IP = 00h

Instruction: SUB M

Postconditions: A Register = 02h
IP = 01h

Micro-Instructions:

Op Code Fetch (3 Clock Cycles)

OR <-- R

AR <-- OR; Memory Address <-- AR; Assert MEMR

DR <-- Memory Data; Memory Address <-- AR;
Assert MEMR

    ALU(A) <-- A; ALU(B) <-- DR;
    ALU(F) <-- ALU(A) - ALU(B);
    A <-- ALU(F)

SUB I data Subtract Immediate From A Register

Addressing Mode: Immediate

Operation: A <-- A - data; IP <-- IP + 2