Contents [Download]

1.0 Introduction [Download]

2.0 Literature Review & Analysis [Download]

    2.1 The Need for a Simple CPU Model that Actually Works
    2.2 Initial CPU Model Specifications
    2.3 Alternative Computer Models
        2.3.1 Lynn CPU
        2.3.2 Streib CPU
        2.3.3 Miller CPU
        2.3.4 McCalla CPU
    2.4 Literature Review Conclusions
    2.5 Final CPU Model Specifications

3.0 Instruction Set [Download]

    3.1 Overview
    3.2 Design Rationale
    3.3 Programmer's Model
    3.4 Instruction Types
    3.5 Addressing Modes
    3.6 Instruction Format
    3.7 Instruction Set Repertoire

4.0 Hardware [Download]

    4.1 Overview
    4.2 Design Rationale
    4.3 Programmer's Model
    4.4 Functional Block Model
    4.5 Detailed Design
        4.5.1 Datapath
        4.5.2 Control Logic

5.0 Operation [Download]

    5.1 The Instruction Cycle
    5.2 Step-By-Step Example of Instruction Execution

6.0 References [Download]

    7.1 Comprehensive Description of Instruction Set [Download]
    7.2 Microprogram Listing [Download Only]
    7.3 PAL Listings [Download Only]
    7.4 Schematics [Download Only]
    7.5 Assembly Drawings [Download Only]

Figure S.1: Programmer's Model of P8 CPU
Figure S.2: Functional Block Diagram of P8 CPU

Figure 2.1: Functional Block Diagram of Lynn CPU
Figure 2.2: Functional Block Diagram of Streib CPU
Figure 2.3: Functional Block Diagram of Miller CPU
Figure 2.4: Functional Block Diagram of McCalla CPU
Figure 2.5: Schematic Diagram of McCalla CPU

Figure 3.1: Distribution of Instruction Frequencies on the Intel 8086
Figure 3.2: Distribution of Addressing Mode Frequencies on the 8086
Figure 3.3: Programmer's Model of P8 CPU
Figure 3.4: Instruction Format for 1-Byte & 2-Byte Instructions

Figure 4.1: Programmer's Model of P8 CPU
Figure 4.2: Functional Block Diagram for P8 CPU
Figure 4.3: Schematic of Datapath with Operand Register, Address Register, Data Register, and Instruction Pointer
Figure 4.4: Schematic of Datapath with A Register, R Register Instruction Register, Z Register, and ALU
Figure 4.5: Block Diagram of Control Store Addressing
Figure 4.6: Control Store Code For Jump If Not Zero (JNZ)
Figure 4.7: Schematic of Control Store
Figure 4.8: PAL 1, PAL 2, and PAL 3
Figure 4.8: Reset Synchronizer

Figure 5.1: Instruction Cycle for SUB 1Ah (Fetch Cycle, Step 1)
Figure 5.2: Instruction Cycle for SUB 1Ah (Fetch Cycle, Step 2)
Figure 5.3: Instruction Cycle for SUB 1Ah (Fetch Cycle, Step 3)
Figure 5.4: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 1)
Figure 5.5: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 2)
Figure 5.6: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 3)
Figure 5.7: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 4)
Figure 5.8: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 5)
Figure 5.9: Instruction Cycle for SUB 1Ah (Execute Cycle, Step 6)

Abstract

Reviews of current textbooks about computer fundamentals, and actual classroom experiences with students, show a need for a working circuit that actually performs the basic functions illustrated by simple, educational CPU models.  Several CPU models in current textbooks were evaluated for implementation, but each of them had at least one feature that eliminated it from consideration. A new CPU model was developed that has been constructed with 23 common ICs. It has an 8-bit data bus, 8-bit address bus, ALU, 2 data registers, 1 condition register, and a microprogrammed control unit. The instruction set is complete, orthogonal, and includes 16 types of instructions: 2 I/O, 4 program control (including conditional branching), 4 data transfer, 3 arithmetic, and 3 logical instructions.  It supports 4 addressing modes: direct, indirect, register, and immediate. All information required to duplicate it, such as schematics and microprogram listings, are included in the downloadable appendixes.

Textbooks for introductory courses about computer organization or computer architecture often contain simple CPU models (usually block diagrams) that illustrate the basic operations common to most CPUs. But, the details of how these functional blocks actually work are rarely discussed. Many students have a background in digital circuit theory. They not only can understand the circuit details, but often want to understand them. Classroom experience with students in the TAC/ABET accredited Electronics Engineering Technology program at Ricks College prompted the development of a working CPU that actually implements the operations described by such a CPU model.

Four "paper" CPU models used in other college classrooms were evaluated for hardware implementation. They were all rejected. Those that were simple enough to implement with about 20 ICs were functionally inadequate to illustrate many principles. The more complete models required 40 or 50 ICs to build.

A new CPU model, called the P8, was developed to combine simplicity with completeness. The programmer's model is shown in Figure S.1. It has three 8-bit registers that are visible to users: the instruction pointer (IP), the A register, and the R register. A 1-bit zero condition register (Z) is also included. Because the IP is 8 bits wide, only 256 memory locations may be addressed. This is ample space for the basic programs normally executed on such a CPU.  There is also a separate space of 256 I/O port addresses.

    CPU Registers

+----------------+
|                | Instruction Pointer (Program Counter)
+----------------+
|                | A Register (Accumulator)
+----------------+
|                | R Register (Data/Address Register)
+-+--------------+
| |                Z Register (Zero Flag Register)
+-+

Memory Space I/O Space

+----------------+             +----------------+
|                | Address 00h |                |
|                |             |                |
|                |             |                |
|                |             |                |
|                | Address FFh |                |
+----------------+             +----------------+

Figure S.1: Programmer's Model of P8 CPU

The P8 CPU has a complete and orthogonal instruction set. The selection of instructions was based on published benchmarks of the instructions used most frequently by the Intel 8086 microprocessor. There are 16 types of P8 instructions. They fall into five categories.

1. Input / Output.  These instructions transfer data between the accumulator and external I/O devices.

    IN = Read Input Port
    OUT = Write Output Port

2. Program Control.  These instructions change the sequence of program execution.  They are often called branch instructions.

    JMP = Unconditional Jump
    JNZ = Jump If Not Zero (Conditional Jump)
    JZ = Jump If Zero (Conditional Jump)
    CMP = Compare (Sets / Resets Zero Bit For Conditional Jumps)

3. Data Transfer.  These instructions cause data in one location (either the internal registers or external memory) to be copied to another location.

    LDA = Load A Register
    LDR = Load R Register
    STA = Store A Register
    STR = Store R Register

4. Arithmetic.  These instructions perform numerical operations on data. Floating point operations are not supported.

    ADD = Add To A Register
    SUB = Subtract From A Register
    DEC = Decrement

5. Logical.  These instructions perform Boolean operations on data, including bit shifting.

    OR = Or With A Register
    INV = Invert & Move To A Register
    SHL = Shift Left & Move To A Register

Four addressing modes are supported. They were also selected as a result of published benchmarks compiled for the 8086 microprocessor.

    1. Direct
    2. Indirect
    3. Register
    4. Immediate

A functional block diagram is shown in Figure S.2. It has been implemented with 23 ICs:

    1 - 74LS74 Dual D Flip Flop                        
    3 - 74LS163 4-Bit Binary Counter
    2 - 74LS181 4-Bit ALU
    3 - 74LS244 Octal 3-State Buffer
    1 - 74LS273 Octal D Flip Flop w/ Clear
    6 - 74LS374 Octal D Flip Flop w/ 3-State Output
    3 - GAL16V8 Programmable Array Logic
    4 - 2764 8K X 8 PROM

The CPU's datapath has an 8-bit internal bus that conveys data between the registers. The A register is the accumulator. It is the destination for all ALU results. The R register can be used for general data storage or as an address pointer for instructions that use indirect addressing. The data register (DR) reads, and writes to, the external data bus. The address register (AR) writes to the external address bus. The instruction pointer (IP) keeps track of where the next instruction in memory is located. The operand register (OR) is used to write operand addresses to AR. The instruction register (IR) holds the 8-bit opcode of the instruction being executed.

The control unit consists of the zero condition register (Z) and the block labeled "control logic". The control logic is a 31-bit control store that contains the microinstructions required to execute each of the P8 CPU's instructions. The correct microinstructions are selected with a combination of inputs from IR, Z, and the microinstruction pointer (MIP), which is a binary counter within the control logic block that sequences through the correct microinstructions for each instruction that is to be executed.

All information required to duplicate the P8 CPU, including schematics, PAL code, and microcode listings, can be found in the downloadable appendixes.


8-Bit

Internal Bus

|                                           +----+
|                                           | DR | Ext Data Bus
+---/-------------------------------------> |OUT |---/---+--/-->
|   8                                       |    |   8   |  8
|                                           +----+       |
|                                           +----+       |
|                                           | DR |       |
|<--------------------------------------/-- | IN |<---/--+
|                                        8  |    |    8
|                                           +----+
|                   +----+                  +----+
|                   | IP |                  | AR | Ext Adr Bus
+---/-------------> |    |---/-----+---/--->|    |---/--------->
|   8               |    |   8     |   8    |    |   8
|                   +----+         |        +----+
|                   +----+         |
|                   | OR |         |
+---/-------------> |    |---/-----+
|   8               |    |   8
|                   +----+
|                   +----+                  +----------+
|                   | IR |                  |          |--> C₀
+---/-------------> |    |---/------------->|  CONTROL | :
|   8               |    |   8              |   LOGIC  | :
|                   +----+                  |          |--> C_N
|                                +----+     |          |--> MEMR
|                                | Z  |     |          |--> MEMW
|                           +-/->|    |--/->|          |--> IOR
|                           | 1  |    |  1  |          |--> IOW
|                   +----+  |    +----+     +----------+
+---/-------------> | ALU|--+
|   8               |    |
|               +-->|    |---/---+    DEFINITIONS:
|               |   +----+   8   |
|     +----+    /8  +----+       |    DR: Data Register
|     | BUF|    |   | A  |       |    AR: Address Register
|<-/--|    |<-/-+-/-|    |<------+    IP: Instruction Pointer
|  8  |    |  8   8 |    |            OR: Operand Register
|     +----+        +----+            IR: Instruction Register
|     +----+        +----+            ALU: Arithmetic Logic Unit
|     | BUF|        | R  |            Z: Zero (Condition Bit) Reg
|<-/--|    |<--/--- |    |<------+    A: A Register (Accumulator)
|  8  |    |   8    |    |       |    R: R Register
|     +----+        +----+       |    BUF: 3-State Buffer
+---/----------------------------+    C₀-C_N: Register Control Bits
    8                                 MEMR: Memory Read Cntrl Bit
                                      MEMW: Memory Write Cntrl Bit
                                      IOR: IO Read Control Bit
                                      IOW: IO Write Control Bit
                                      /8: 8-Bit Parallel Bus
                                      /1: 1-Bit Line

Figure S.2: Functional Block Diagram of P8 CPU

[Back to Top][Back to Table of Contents][Next Section ==>]