ECE 224: Hardware Project Design Notes

Brief Description

This circuit simulates the rolling of two dice.  It is implemented with two mod-6 counters that produce 36 different states in the count sequence.  Each state corresponds to one of the number combinations to be displayed on the dice. The design shown here was originally published in the 3rd edition of "PAL Handbook" by J. Birkner and V. Coli of Monolithic Memories, Inc.  The book is no longer in print.

The faces of each die are represented by LEDs that illuminate in the appropriate pattern for each state.  The two counters must be implemented with a Programmable Logic Device (PLD).  You must connect this display circuits to the output of the counters.  You will also have to build a clock circuit to drive the counters. 

The circuit should operate with a +5 V power source.  You may connect it to a bench power supply, or, optionally, put a +5 V regulator on your circuit board.  A diagram that shows how to configure the voltage regulator may be seen by following this hyperlink.

Much of the design for these "electronic dice" will be given here, but you must fill in some of the "blanks" and actually make it work.  The CSE faculty will not help you troubleshoot this circuit!  Part of the learning experience is to solve any problems with the help of your peers.  Each student must construct his or her own circuit, but you are encouraged help each other.

Design Using Standard TTL

In one die, seven LEDs make up the display.

Notice they can be connected so that only four lines are required to drive them.   (The resistor values shown are only suggestions.  Is safe to use any resistors that are close to those shown above.)  

The LEDs are turned on when the appropriate line(s) is/are driven low (indicated by the "_bar" suffix).  Because there are four lines to be driven, it is necessary to use four flip-flops for each die.   (D-type flip-flops will be used in this example, because the PLD has internal D FFs.)  By using the inverting output of the flip-flop, we can use positive logic in the design.  That is, a logical "1" at a Q output represents an LED being turned on by the inverted Q output (Q').

The state transition diagram shows the sequence in which the LEDs should turn on (Q4 Q3 Q2 Q1):  

(0100) --> (0010) --> (1100) --> (1010) --> (1110) --> (1011) --> (0100) . . .

Notice that the count sequence is always the same.  This circuit does not generate a random number to be displayed.  The "randomness" comes from the fact that the circuit sequences so rapidly, it is impossible for a human being to stop the clock at any given state.

Here is the state transition table:

Present State     Next State          Required D FF Input

Q4 Q3 Q2 Q1       Q4+ Q3+ Q2+ Q1+     D4 D3 D2 D1

0  0  0  0        X   X   X   X       X  X  X  X
0  0  0  1        X   X   X   X       X  X  X  X
0  0  1  0        1   1   0   0       1  1  0  0
0  0  1  1        X   X   X   X       X  X  X  X
0  1  0  0        0   0   1   0       0  0  1  0
0  1  0  1        X   X   X   X       X  X  X  X
0  1  1  0        X   X   X   X       X  X  X  X
0  1  1  1        X   X   X   X       X  X  X  X
1  0  0  0        X   X   X   X       X  X  X  X
1  0  0  1        X   X   X   X       X  X  X  X
1  0  1  0        1   1   1   0       1  1  1  0
1  0  1  1        0   1   0   0       0  1  0  0
1  1  0  0        1   0   1   0       1  0  1  0
1  1  0  1        X   X   X   X       X  X  X  X
1  1  1  0        1   0   1   1       1  0  1  1
1  1  1  1        X   X   X   X       X  X  X  X

Using K-maps, equations  for D1, D2, D3, and D4 are obtained.   Notice that the simplest possible logic equations were not generated.  This was to ensure a path to a valid state from all invalid states.  (This is one of the "blanks" you will have to fill in for yourself.)

D1 = Q1'Q2Q3

D2 = Q1'Q3 + Q1'Q4

D3 = Q3'

D4 = Q1'Q2 + Q1'Q4

These equations satisfy the requirements for one die.  By substituting Q5-Q8 for Q1-Q4 and D5-D8 for D1-D4, we have the following equations:

D5 = Q5'Q6Q7

D6 = Q5'Q7 + Q5'Q8

D7 = Q7'

D8 = Q5'Q6 + Q5'Q8

Because this is a synchronous design, the clocks of the two counters (dice) are common.   If the same equations are used for both dice, there will only be six different states.  To get around this, the first die is allowed to go through each of the six states, incrementing with each clock pulse.  The second die is inhibited from incrementing except when the first die goes from "1011" to "0100" (the sixth state to the first state).  At this time, the second die is allowed to increment one time.  Notice, in the state transition table, that whenever output Q1 is high, the next clock should increment the second die.  Whenever Q1 is low, the second die should remain the same.  This results in the following equations for the entire design:

D1 = Q1'Q2Q3

D2 = Q1'Q3 + Q1'Q4

D3 = Q3'

D4 = Q1'Q2 + Q1'Q4

D5 = Q1'Q5 +Q1Q5'Q6Q7

D6 = Q1'Q6 + Q1Q5'Q7 + Q1Q5'Q8

D7 = Q1'Q7 + Q1Q7'

D8 = Q1'Q8 + Q1Q5'Q6 + Q1Q5'Q8

From these equations, the circuit can be realized using D FFs and simple logic gates.

Design Using PLD Devices

A PLD with 8 registered outputs is required.  Two good choices would be either the PAL16R8 or the GAL16V8.  The PAL is a little less expensive, but it can only be programmed once.  You might want to consider the GAL for this project, because if you make a programming mistake, you can simply erase it and try again. 

The equations developed above can be used here without change.   Note that the pinouts, in the diagram below, are chosen to convenience layout of the board.  Also, the clock circuit should look familiar.  It is similar to the blinker circuit in Lab 2, only much faster.

NOTE: If you buy a GAL made by Lattice, your "dice" will probably "roll" occasional "0s" or "7s", which is impossible for real dice.  Other brands of GAL16V8 do not do this.  If this glitch is unacceptable to you, and you cannot obtain a different brand of GAL, use a PAL16R8 instead.  If you do this, test your circuit and program with one of the GALs in the lab before burning your PAL.

Now, there is one more "blank" for you to fill in.  The logic equations for this circuit must be incorporated into your CUPL source file.  Once it is compiled, and downloaded into the PLD, you can do your final verification testing. 

TIME SAVER:  Don't wait until the end of the semester to start this project!   You will be inundated with assignments from all your classes and time will be scarce.  You will not understand very much of the synchronous counter design presented here until after Lab 10, but you will be able to actually build this circuit after only Lab 2.  Start on it then, and program the PLD later, after you learn how.  (HINT: The PLD code (the last "blank") for this project is available on the Software Downloads page in this web site.)

ALTERNATIVE OSCILLATOR:  Some students have found that a different clock circuit is easier to build and troubleshoot than the one shown above (with discrete transistors).  It uses a 555 IC timer with a resistor-capacitor network.  You can find the alternative oscillator (clock) design by following this hyperlink.  Just connect the Clock Output (pin 3) of the 555 timer to the CLK input (pin 1) of the PLD and put your N/O switch in series with the +5V source. The 0.1 uF capacitor will reduce the frequency too much, so leave it out.